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copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. advanced pwm and triple linear power controllers general description applications ? ? ? ? ? motherboard power regulation for computers functional the apw6021 provides the power control and pro- tection for four output voltages in high-performance, graphics intensive microprocessor and computer applications. the ic integrates voltage-mode pwm controller and three linear controllers, as well as the monitoring and protection functions into a 28-pin soic package. the pwm controller regulates the micro- processor core voltage with a synchronous-rectified buck converter. the linear controllers regulate the computer system?s agp 1.5v or 3.3v bus power, the 1.5v gtl bus power, and the 1.8v power for the north/south bridge core voltage and/or cache memory circuits. the apw6021 includes an intel- compatible, ttl 5-input digital-to-analog converter (dac) that adjusts the core pwm output voltage from 1.3 v dc to 2.05 v dc in 0.05v steps and from 2.1 v dc to 3.5 v dc in 0.1v increments. the precision reference and voltage-mode control provide 1 % static regulation. the agp bus power linear controller?s output (v out2 ) is user-selectable, through a ttl-com- patible signal applied at the select pin, for levels of 1.5v or 3.3v with 3 % accuracy. based on the sta- tus of the fix pin, the other two linear regulators pro- vide either fixed output voltages of 1.5v 3 % (v out3 ) and 1.8v 3 % (v out4 ), or user-adjustable by means of an external resistor divider. all linear controllers can employ either n-channel mosfets or bipolar npns for the pass transistor. the apw6021 monitors all the output voltages. a single power good signal is issued when the core is within 10 % of the dac setting and all other outputs are above their under-voltage levels. additional built- in over-voltage protection for the core output uses the lower mosfet to prevent output voltages above 115 % of the dac setting. the pwm controller?s over- current function monitors the output current by using the voltage drop across the upper mosfet?s r ds(on) . ? ? ? ? ? 4 regulated voltages are provided ? ? ? ? ? microprocessor core (1.3v to 3.5v) ? ? ? ? ? agp bus (1.5v or 3.3v) ? ? ? ? ? memory (1.8v) ? ? ? ? ? gtl bus (1.5v) ? ? ? ? ? linear controllers drives with both mosfet and bipolar series pass transistors ? ? ? ? ? fixed or externally resistor-adjustable linear outputs (fix pin) ? ? ? ? ? simple single-loop control design ? ? ? ? ? voltage-mode pwm control ? ? ? ? ? fast pwm converter transient response ? ? ? ? ? high-bandwidth error amplifier ? ? ? ? ? full 0 % to 100 % duty ratio ? ? ? ? ? excellent output voltage regulation ? ? ? ? ? core pwm output: 1 % over temperature ? ? ? ? ? other outputs: 3 % over temperature ? ? ? ? ? ttl-compatible 5- bit dac microprocessor core output voltage selection ? ? ? ? ? wide range - 1.3v dc to 3.5 v dc ? ? ? ? ? power-good output voltage monitor ? ? ? ? ? over-voltage and over-current fault monitors ? ? ? ? ? switching regulator does not require extra current sensing element, uses mosfet?s r ds(on) ? ? ? ? ? small converter size ? ? ? ? ? constant frequency operation ? ? ? ? ? 200khz free-running oscillator; program- mable from 50khz to over 1mhz
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 2 pin description ordering information vcc fault/ rt 1 2 3 4 5 6 7 8 sd 12 11 10 9 ss 16 15 13 14 17 18 19 20 24 23 22 21 28 27 26 25 lgate ocset vsen1 pgnd fb comp ugate phase drive3 gnd vaux drive4 vid4 vid3 vid0 vid1 vid2 drive2 fix pgood vsen2 select vsen4 vsen3 apw6021 package code k : sop - 28 temp. range c : 0 to 70 c handling code tu : tube tr : tape & reel handling code temp. range package code absolute maximum ratings symbol parameter rating unit v cc supply voltage 15 v v boot ?v phase boot voltage 15 v v i , v o input , output or i/o voltage gnd -0.3 v to v cc +0.3 v t a operating ambient temperature range 0 to 70 c t j junction temperature range 0 to 125 c t stg storage temperature range -65 to +150 c t s soldering temperature 300 ,10 seconds c
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 3 block diagram pgood power-on reset (por) vcc 200 a 1.10 soft start & fault logic + - gate control + - pwm comp1 synch drive ov dacout ugate phase vcc lgate pgnd comp fb ss ocset vsen1 error amp1 pwm1 vcc inhibit oc1 driver1 vaux luv linear under- voltage + - + - drive3 drive 4 + - vid0 ttl d/a converter (dac) vid1 vid2 vid3 vid4 + - 1.26v + - + - + - + - + - oscillator fault/ rt 0.90 1.15 vcc 4.5v 28 a fault inhibit 0.75 vaux vsen 4 drive2 vsen2 select gnd 0.75 sd fix vsen3 + - + - 1.5v or 3.3v + - thermal characteristics symbol parameter value unit r ja thermal resistance in free air soic soic (with 3in 2 of copper) 75 65 c/w
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 4 electrical characteristics (recommended operating conditions, unless otherwise noted) refer to block and simplified power system diagrams, and typical application schematic apw6021 symbol parameter test conditions min. typ. max. unit v cc supply current i cc nominal supply current ugate, lgate, drive2, drive3, and drive4 open 9ma power-on reset rising vcc threshold vocset=4.5v 10.4 v falling vcc threshold vocset=4.5v 8.2 v rising vaux threshold vocset=4.5v 2.5 v vaux threshold hysteresis vocset=4.5v 0.5 v rising v ocset threshold 1.26 v oscillator f ocs free running frequency rt= open 185 200 215 khz ? v osc ramp amplitude rt= open 1.9 v p-p dac and bandgap reference dac(vid0-vid4) input low voltage 0.8 v dac(vid0-vid4) input high voltage 2.0 0.8 v dacout voltage accuracy -1.0 +1.0 % v bg bandgap reference voltage 1.265 v bandgap reference tolerance -2.5 +2.5 % linear regulators (out2, out3, and out4) regulation (all linears) 3 % vreg 2 vsen2 regulation voltage select < 0.8v 1.5 v vreg 2 vsen2 regulation voltage select > 2.0v 3.3 v vreg 3 vsen3 regulation voltage 1.5 v vreg 4 vsen4 regulation voltage 1.8 v vren uv under-voltage level (vsen/ vreg) vsen rising 75 % under-voltage hysteresis (vsen/ vreg) vsen falling 7 % output drive current (all liners) vaux-v drive >0.6v 20 40 ma
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 5 electrical characteristics cont. functional pin description drive2 (pin 1) connect this pin to the gate of an external mosfet. this pin provides the drive for the agp regulator?s pass transistor. fix (pin 2) grounding this pin bypasses the internal resistor di- viders that set the output voltage of the 1.5v and 1. 8v linear regulators. this way, the output voltage of the two regulators can be adjusted from 1.26v up to the input voltage (+3.3v or +5v) by way of an exter- nal resistor divider connected at the corresponding vsen pin. the new output voltage set by the exter- nal resistor divider can be determined using the fol- lowing formula: v out =1.265v [ 1+r out / r gnd ] where r out is the resistor connected from vsen to the output of the regulator, and r gnd is the resistor connected from vsen to ground. left open, the fix pin is pulled high, enabling fixed output voltage operation. apw6021 symbol parameter test conditions min. typ. max. unit synchronous pwm controller error amplifier dc gain 88 db gbwp gain-bandwidth product 15 mhz sr slew rate comp=10pf 6 v/ s pwm controller gate driver i ugate ugate source v cc =12v, v ugate =6v 1 a r ugate ugate sink v ugate1-phase =1v 3.5 ? i lgate lgate source v cc =12v, v lgate =1v 1 a r lgate lgate sink v lgate = 1v 3 ? protection vsen1 over-voltage (vsen1/dacout) vsen1 rising 115 120 % i ovp fault souring current v fault/rt =2.0v 8.5 ma i ocset ocset1 current source v ocset = 4.5v dc 170 200 230 a i ss soft start current 28 a power good vsen1 upper threshold (vsen1/dacout) vsen1 rising 108 110 % vsen1 under voltage (vsen1/dacout) vsen1 rising 92 94 % vsen1 hysteresis (vsen1 /dacout) upper /lower threshold 2 % v pgood pgood voltage low i pgood = -4ma 0.8 v
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 6 functional pin description cont. vid4, vid3, vid2, vid1, vid0 (pins 3, 4, 5, 6 and 7) vid0-4 are the ttl-compatible input pins to the 5-bit dac. the logic states of these five pins program the internal voltage reference (dacout). the level of dacout sets the microprocessor core converter output voltage, as well as the corresponding pgood and ovp thresholds. pgood (pin 8) pgood is an open collector output used to indicate the status of the output voltages. this pin is pulled low when the synchronous regulator output is not within 10% of the dacout reference voltage or when any of the other outputs are below their under- voltage thresholds. the pgood output is open for?11111? vid code. sd (pin 9) this pin shuts down all the outputs. a ttl- compatible, logic level high signal applied at this pin immediately discharges the soft-start capacitor, disabling all the outputs. dedicated internal circuitry insures the core output voltage does not go negative during this process. when re-enabled, the ic under- goes a new soft-start cycle. left open, this pin is pulled low by an internal pull-down resistor, enabling operation. vsen2 (pin 10) connect this pin to the output of the agp linear regulator. the voltage at this pin is regulated to the level predetermined by the logic-level status of the select pin. this pin is also monitored for under- voltage events. select (pin 11) this pin determines the output voltage of the agp bus linear regulator. a low ttl input sets the output voltage to 1.5v, while a high input sets the output voltage to 3.3v. ss (pin 12) connect a capacitor from this pin to ground. this capacitor, along with an internal 28 a current source, sets the soft-start interval of the converter. fault / rt (pin 13) this pin provides oscillator switching frequency adjustment. by placing a resistor (r t ) from this pin to gnd, the nominal 200khz switching frequency is in- creased according to the following equation: fs =200khz + 5 10 6 / r t (k ?) (r t to gnd) conversely, connecting a resistor from this pin to vcc reduces the switching frequency according to the fol- lowing equation: fs =200khz + 4 10 7 / r t (k ?) (r t to 12v) nominally, the voltage at this pin is 1.26v. in the event of an over-voltage or over-current condition, this pin is internally pulled to vcc. vsen4 (pin 14) connect this pin to the output of the linear 1.8v regulator. this pin is monitored for undervoltage events. drive4 (pin 15) connect this pin to the gate of an external mosfet. this pin provides the drive for the 1.8v regulator?s pass transistor. vaux (pin 16) this pin provides boost current for the linear regula- tors? output drives in the event bipolar npn transis- tors (instead of n-channel mosfets) are employed as pass elements. the voltage at this pin is moni- tored for power-on reset (por) purposes. gnd (pin 17) signal ground for the ic. all voltage levels are mea- sured with respect to this pin.
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 7 drive3 (pin 18) connect this pin to the gate of an external mosfet. this pin provides the drive for the 1.5v regulator?s pass transistor. vsen3 (pin 19) connect this pin to the output of the 1.5v linear regulator. this pin is monitored for under-voltage events. comp and fb (pin 20, and 21) comp and fb are the available external pins of the pwm converter error amplifier. the fb pin is the in- verting input of the error amplifier. similarly, the comp pin is the error amplifier output. these pins are used to compensate the voltage-mode control feedback loop of the synchronous pwm converter. vsen1 (pin 22) this pin is connected to the pwm converter?s output voltage. the pgood and ovp comparator circuits use this signal to report output voltage status and for over- voltage protection. ocset (pin 23) connect a resistor from this pin to the drain of the respective upper mosfet. this resistor, an internal 200 a current source, and the upper mosfet?s on- resistance set the converter over-current trip point. an over-current trip cycles the soft-start function. the voltage at this pin is monitored for power-on re- set (por) purposes and pulling this pin low with an open drain device will shutdown the ic. pgnd (pin 24) this is the power ground connection. tie the syn- chronous pwm converter?s lower mosfet source to this pin. functional pin description cont. lgate (pin 25) connect lgate to the pwm converter?s lower mosfet gate. this pin provides the gate drive for the lower mosfet. phase (pin 26) connect the phase pin to the pwm converter?s up- per mosfet source. this pin represents the gate drive return current path and is used to monitor the voltage drop across the upper mosfet for over-cur- rent protection. ugate (pin 27) connect ugate pin to the pwm converter?s upper mosfet gate. this pin provides the gate drive for the upper mosfet. vcc (pin 28) provide a 12v bias supply for the ic to this pin. this pin also provides the gate bias charge for all the mosfets controlled by the ic. the voltage at this pin is monitored for power-on reset (por) purposes.
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 8 table 1 output voltage program pin name pin name vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 01111 1.3 11111 0 01110 1.35 11110 2.1 01101 1.4 11101 2.2 01100 1.45 11100 2.3 01011 1.5 11011 2.4 01010 1.55 11010 2.5 01001 1.6 11001 2.6 01000 1.65 11000 2.7 00111 1.7 10111 2.8 00110 1.75 10110 2.9 00101 1.8 10101 3.0 00100 1.85 10100 3.1 00011 1.90 10011 3.2 00010 1.95 10010 3.3 00001 2.00 10001 3.4 00000 2.05 10000 3.5 simplified power system diagram linear controller linear controller pwm controller apw6021 +5v in linear controller q1 q2 v out3 q3 v out2 +3.3v in q4 q5 v out4 v out1
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 9 typical application apw6021 ocset pgood ugate phase lgate pgnd vsen1 fb comp fault/ rt c ss gnd vsen2 drive3 vcc +12v in +3.3v in v out2 typedet c in +5v in power good q1 v out1 1.3v to 3.5v c out1 l out1 q2 l in q4 c out3 1.5v v out3 vid1 vid3 vid4 vid2 vid0 ss 1.5v or 3.3v c out2 select vaux vsen3 q5 c out4 fix drive4 vsen4 1.8v v out4 q3 drive2
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 10 package information so ? 300mil ( reference jedec registration ms-013) n 12 3 e h d l gauge plane 1 e b a1 a millimeters variations- d inches variations- d dim min. max. variations min. max. dim min. max. variations min. max. a2.35 2.65 so-16 10.10 10.50 a 0.093 0.1043 so-16 0.398 0.413 a1 0.10 0.30 so-18 11.35 11.76 a1 0.004 0.0120 so-18 0.447 0.463 b 0.33 0.51 so-20 12.60 13 b 0.013 0.020 so-20 0.496 0.512 d see variations so-24 15.20 15.60 d see variations so-24 0.599 0.614 e 7.40 7.60 so-28 17.70 18.11 e 0.2914 0.2992 so-28 0.697 0.713 e 1.27bsc so-14 8.80 9.20 e 0.050bsc so-14 0.347 0.362 h 10 10.65 h 0.394 0.419 l 0.40 1.27 l 0.016 0.050 n see variations n see variations 10 8 10 8
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 11 classification reflow profiles package reflow conditions refolw condition (ir/ convection or vpr reflow) physical specifications terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb) lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. packaging 1000 devices per reel convection or ir/ convection vpr average ramp-up rate(183 c to peak) 3 c/second max. 10 c /second max. preheat temperature 125 25 c) 120 seconds max. temperature maintained above 183 c 60 ~ 150 seconds time within 5 c of actual peak temperature 10 ~ 20 seconds 60 seconds peak temperature range 220 +5/-0 c or 235 +5/-0 c 215~ 219 c or 235 +5/-0 c ramp-down rate 6 c /second max. 10 c /second max. time 25 c to peak temperature 6 minutes max. pkg. thickness 2.5mm and all bags pkg. thickness < 2.5mm and pkg. volume 350 mm3 pkg. thickness < 2.5mm and pkg. volume < 350mm3 convection 220 +5/-0 c convection 235 +5/-0 c vpr 215-219 c vpr 235 +5/-0 c ir/convection 220 +5/-0 c ir/convection 235 +5/-0 c reference jedec standard j-std-020a april 1999 pre-heat temperature 183 c peak temperature time temperature
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 12 tape & reel dimensions reliability test program test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms , i tr > 100ma application a b c j t1 t2 w p e sop- 28 330 1 62 1.5 12.75 0. 5 2 0.6 24.4 0.2 2 0.2 24 0.3 12 0.1 1.75 0.1 application f d d1 po p1 ao bo ko t sop- 28 11.5 0.1 1.5 +0.1 1.5+ 0.25 4.0 0.1 2.0 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 t ao e w po p ko bo d1 d f p1 a j b t2 t1 c
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 apw6021 www.anpec.com.tw 13 cover tape dimensions customer service carrier width 24 cover tape width 21.3 anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369

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